1. Field of the Invention
The present invention relates to an analog buffer, and more particularly, to an analog buffer and a method of fabricating the same that are capable of reducing power consumption.
2. Description of the Related Art
A liquid crystal display device displays a picture by controlling the light transmittance of a liquid crystal material having a dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a drive circuit for driving the liquid crystal panel. As shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 2r having a pixel matrix, a gate driver 4r for driving gate lines GL1 to GLn of the liquid crystal panel 2r, a data driver 6r for driving data lines DL1 to DLm of the liquid crystal panel 2r and a timing controller 8r for controlling a driving timing of the gate driver 4r and the data driver 6r. The liquid crystal panel 2r includes the pixel matrix having pixels 12r formed at each area defined by each intersection of gate lines GL and data lines DL. Each of the pixels 12r has a liquid crystal cell Clc that controls light transmittance according to a pixel signal and a thin film transistor TFT that drives the liquid crystal cell Clc.
When the thin film transistor TFT receives a gate driving signal from the gate line GL, i.e., a gate high voltage VGH, the thin film transistor TFT is turned-on to supply a video signal from the data line DL to the liquid crystal cell Clc. Moreover, when the thin film transistor TFT receives a gate low voltage VGL from the gate line GL, the thin film transistor TFT is turned-off, thereby maintaining a video signal charged to the liquid crystal cell Clc. The liquid crystal cell Clc can be equivalently represented as a capacitor. The liquid crystal cell Clc includes a common electrode and a pixel electrode connected to the TFT wherein a liquid crystal material is inserted between the common electrode and the pixel electrode. The liquid crystal cell Clc further includes a storage capacitor (not shown) for stably maintaining the video signal charged thereto until a next video signal is charged. The liquid crystal cell Clc varies the arrangement of liquid crystal materials with a dielectric anisotropy in accordance with the video signal charged through the TFT, thereby controlling the light transmittance. Accordingly, the liquid crystal cell Clc represents gray levels.
The gate driver 4r shifts a gate start pulse (GSP) from a timing controller 8r in accordance with a gate shift clock (GSC) to sequentially supply a scan pulse of the gate high voltage VGH to the gate lines GL1 to GLm. Moreover, the gate driver 4r supplies the gate low voltage VGL during a scan pulse of the gate high voltage VGH is not supplied to the gate lines GL1 to GLm.
The data driver 6r shifts a source start pulse (SSP) from the timing controller 8r in accordance with a source shift clock (SSC), thereby generating a sampling signal. Further, the data driver 6r latches a video data RGB input by the signal SSC in accordance with the sampling signal, and then supplies the latched video data by a line unit in response to a source output enable (SOE) signal. Then, the data driver 6r converts digital video data RGB supplied by the line unit to analog video signals using gamma voltages, which are different each other, supplied from a gamma voltage, thereby supplying the analog video signals to the data lines DL1 to DLm. At this time, the data driver 6r determines the polarity of the video signals in response to the polarity controlling signal (POL) from the timing controller 8r at the time of the conversion of the digital video data to the analog video signals.
The timing controller 8r generates the signals GSP and GSC for controlling the gate driver 4r and also generates a source start signal SSP, a source shift clock SSC, a source output enable signal SOE, and the signal POL signals for controlling the data driver 6r. More specifically, the timing controller 8r generates a variety of control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, POL and the like using a data enable DE signal representing an effective data interval, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync and a dot clock (DCLK) to determine the transmission timing of the pixel data RGB.
In the liquid crystal display device configured as described above, the data driver 6r includes an analog buffer for preventing a distortion of the video signal supplied to the data line in accordance with an amount of RC load on the data line. The gate driver 4r also includes an analog buffer for preventing a distortion of the gate driving signal supplied to the gate line in accordance with an amount of RC load on the gate line. In general, an amplifier (OP-AMP) is mainly used for the analog buffer. However, a scheme having a simplified circuit configuration using an inverter has been recently proposed.
For instance, a paper “AMLCD '02”, PP21-24, published by Toshiba describes an analog buffer which employs three inverters as shown in FIG. 2. The analog buffer shown in FIG. 2 includes: first to third inverters 3, 5 and 7 which are connected in series between an input line and an output line; first to third capacitors 2, 4 and 6 which are connected in series to input terminals of the first to the third inverter 3, 5 and 7, respectively; a first switch 1 connected between the input line and the first capacitor 2; second to fourth switches 8, 9 and 10 which are connected between input terminals and output terminals of the first to the third inverters 3, 5 and 7, respectively; and a fifth switch 11 connected between the input line and the output line.
FIGS. 3A and 3B are a driving waveform diagram and a power consumption waveform diagram for the analog buffer shown in FIG. 2, respectively.
The second to the fourth switches 8, 9 and 10 of FIG. 2 for initializing the first to the third inverters 3, 5 and 7 are turned-on by a reset pulse RESET as shown in FIG. 3A. Accordingly, the input and output terminals of the first to the third inverters 3, 5 and 7 are shorted so that the first to the third inverters 3, 5 and 7 are initialized with a value of an intermediate voltage Vm of a power source. Also, the first switch 1 for supplying an input voltage Vin is turned-on to supply the input voltage Vin, as shown in FIG. 3A, to the first capacitor 2. Accordingly, a difference voltage of the input voltage Vin and the intermediate voltage Vm applied to the initialized first inverter 3 is charged in the first capacitor 2. Subsequently, the fifth switch 11 used for a feedback is turned-on so that the output voltage Vout corresponding to the input voltage Vin is monitored in the output line.
Since the analog buffer is organized with only the inverters, it has a simple configuration as compared with a typical analog buffer implemented using the amplifiers OPAMP. However, in the analog buffer shown in FIG. 2, the first to the third inverters 3, 5 and 7 should maintain the intermediate voltage Vm after charging the input voltage Vin in the output line. Accordingly, there always exists a stand-by current caused by the first to the third inverters 3, 5 and 7. As a result, a power of about −80 μW (microwatts) is dissipated after charging the input voltage Vin, as shown in FIG. 3B. The power consumption is significantly increased with increasing numbers of inverters.